The present invention relates to semiconductor memory devices and more particularly, to nonvolatile memory devices.
A flash memory device, as a kind of the nonvolatile memory device, is regarded as an electrically erasable programmable read only memory (EEPROM) in which plural memory sectors are erasable or programmable by a single programming operation. This means that while a typical EEPROM is only able to be erased or programmed for a single memory block at a time, the flash memory device is operable in high frequency and efficiency in the condition that a system employing the flash memory reads and writes data with other memory blocks at the same time. Flash memories and EEPROMs have limited lifetimes because insulation films around charge storage elements thereof are usually destroyed by erasing data several hundreds or thousands times.
The flash memory device stores information in a silicon chip thereof even without any power being applied. This means that the information stored in the chip is retained even if the power is interrupted. In addition, the flash memory device has resistance against physical shocks and provides a fast access time for reading. Owing to such merits, the flash memory device is usually employed as a storage unit in an apparatus powered by a battery.
Flash memory devices may be classified into NOR and NAND type devices, in accordance with the circuit patterns of the logic gates in the devices.
A flash memory has memory cells including a transistor array that stores information or data, each cell storing 1-bit of information. Meantime, a multi-level cell is designed to store more than one bit by varying the amount of charges accumulated in a floating gate thereof.
In a NOR flash memory device, each cell is similar to a typical MOSFET transistor, except that it is constructed with two gates therein. The first one is a control gate (CG) that is the same as that of other MOS transistors, while the second one is referred to as a floating gate (FG) that is electrically isolated, being surrounded by an insulation film. The floating gate is interposed between the control gate and the substrate (or a bulk material). Since the floating gate is electrically isolated by the insulation film, electrons are held and remain in the floating gate to store information. Electrons settled in the floating gate cause an electric field from the control gate to be varied (partially offsetting the electric field), which changes a threshold voltage of the memory cell. Thus, when a specific voltage is applied to the control gate to read data from the cell, a current may or may not flow through the memory cell in accordance with the threshold voltage thereof. Such current flow is regulated by the amount of charge accumulated in the floating gate. A data value of ‘1’ or ‘0’ is detected in accordance with whether or not there is current flow which corresponds to the data stored in the memory cell. In the multi-level cell storing more than one bit per cell, the amount of electrons held in the floating gate may be detected according to the amount of current flowing through the memory cell, rather than the presence or absence of current, in practice.
A NOR flash memory cell is programmed by applying a program voltage to a control gate, applying a high voltage of about 5˜6V to a drain, and grounding a source, which stores in the cell a specific data value. With such a bias condition, a large current flows from the drain to the source. This programming scheme is referred to as hot electron injection. In erasing the NOR flash memory cell, a high voltage gap is established between the control gate and the substrate (or bulk), which induces a Fowler-Nordheim tunneling effect to release the electrons from the floating gate. A cell array of the NOR flash memory device is usually divided into blocks or sectors that are erased as a unit. Memory cells belonging to a block are erased at the same time in a single erasing cycle. Otherwise, a programming operation in the NOR flash memory device is carried out in the unit of a byte or word.
For the purpose of regulating a distribution profile of threshold voltages of programmed memory cells, an incremental step pulse programming scheme (ISPP) is generally employed. By the ISPP scheme, as illustrated in FIG. 1, the program voltage VWL applied to a wordline is stepped up during an iteration of programming loops over operating cycles in a programming mode. Each programming loop includes a programming period and a program verifying period, as is well known. The program voltage VWL increases by a predetermined step voltage Δ V. During the sequence of the programming operation, at each program loop the threshold voltage Vt of the cell being programmed is increased by the predetermined voltage step Δ V. Therefore, the step voltage Δ V needs to be made smaller in order to narrow the width of the distribution profile of the threshold voltages. As the step voltage Δ V is made smaller, the number of programming loops becomes larger. Thus, the number of the programming loops is determined so as to optimize the threshold voltage distribution profile without limiting the performance of the memory device.
An exemplary programming scheme for a nonvolatile memory device is disclosed in U.S. Pat. No. 6,266,270 entitled “Non-volatile semiconductor memory and programming method of the same.” Also, circuits for generating program voltages have been proposed in U.S. Pat. No. 5,642,309, entitled “Auto-program circuit in a nonvolatile semiconductor memory device,” and in Korean Patent Publication No. 2002-39744 entitled “Flash memory device capable of preventing disturb and method of programming the same.”
In programming a NOR flash memory device by means of the ISPP scheme, as aforementioned, a wordline voltage of 10V is applied to the control gate of the flash memory cell, a bitline voltage of 5˜6V is applied to the drain, and a voltage less than 0V (e.g., −1V) is applied to the bulk (or substrate) of the flash cell. In general, the current flowing through the flash memory cell, Icell, is (VGS−Vt)2, where Vt is proportional to a threshold voltage of the flash memory cell and VGS is a gate-to-source voltage of the flash memory cell. The bitline voltage is generated and maintained by a charge pump (not shown). If the amount of current flowing through the memory cell is greater than the capacity of the charge pump for the bitline voltage, the bitline voltage drops below a predetermined voltage level. With a drop of the drain voltage (that is, the bitline voltage), it becomes difficult for the threshold voltage of the flash cell to increase up to a desired level in a certain programming loop, as shown by the broken line in FIG. 1. In particular, during a programming operation with the ISPP scheme, as the difference between the wordline voltage and the threshold voltage becomes larger in accordance with the repetition of the programming loops, the programming characteristic may be gradually degraded to result in programming failures.
Accordingly, it would be desirable to provide a nonvolatile memory device with improved programming characteristics.
In particular, it would be desirable to provide an advanced technique to prevent programming failure due to a drop of the bitline voltage during a programming operation.
It would also be desirable to provide a nonvolatile memory device able to maintain a bitline voltage with stability during a programming operation.
It would further be desirable to provide a nonvolatile memory device variably controlling the capacity of a charge pump for a bitline voltage in a programming operation.